PIER
 
Progress In Electromagnetics Research
ISSN: 1070-4698, E-ISSN: 1559-8985
Home | Search | Notification | Authors | Submission | PIERS Home | EM Academy
Home > Vol. 115 > pp. 223-242

ELECTROTHERMAL EFFECTS IN HIGH DENSITY THROUGH SILICON VIA (TSV) ARRAYS

By W.-S. Zhao, X.-P. Wang, and W.-Y. Yin

Full Article PDF (966 KB)

Abstract:
Electrothermal effects in various through silicon via (TSV) arrays are investigated in this paper. An equivalent lumped-element circuit model of a TSV pair is derived. The temperature-dependent TSV capacitance, silicon substrate capacitance and conductance are examined for low-, medium-, and high-resistivity silicon substrates, respectively. The partial-element equivalent-circuit (PEEC) method is employed for calculating per-unit-length (p.u.l.) resistance, inductance, insertion loss and characteristic impedances of copper and polycrystalline silicon (poly-Si) TSV arrays, and their frequency- and temperature-dependent characteristics are treated rigorously. The modified time-domain finite-element method (TD-FEM), in the presence of a set of periodic differential-mode voltage pulses, is also employed for studying transient electrothermal responses of 4- and 5-TSV arrays made of different materials, with their maximum temperatures and thermal crosstalk characterized thoroughly.

Citation:
W.-S. Zhao, X.-P. Wang, and W.-Y. Yin, "Electrothermal Effects in High Density through Silicon via (Tsv) Arrays," Progress In Electromagnetics Research, Vol. 115, 223-242, 2011.
doi:10.2528/PIER11030503
http://www.jpier.org/PIER/pier.php?paper=11030503

References:
1. Koyanagi, M., T. Fukushima, and T. Tanaka, "High-density through silicon vias for 3-D LSIs," Proc. IEEE, Vol. 97, No. 1, 49-59, Jan. 2009.
doi:10.1109/JPROC.2008.2007463

2. Katti, G., M. Stucchi, K. D. Meyer, and W. Dehaene, "Electrical modeling and characterization of through silicon via for three-dimensional ICs," IEEE Trans. Electron Devices, Vol. 57, No. 1, 256-262, Jan. 2010.
doi:10.1109/TED.2009.2034508

3. Ramaswami, S., et al., "Process integration considerations for 300nm TSV manufacturing," IEEE Trans. Device Mater. Rel., Vol. 9, No. 4, 524-528, Dec. 2009.
doi:10.1109/TDMR.2009.2034317

4. Bandyopadhyay, T., R. Chatterjee, D. Chung, M. Swaminathan, and R. Tummala, Electrical modeling of through silicon and package vias, IEEE Int. Conf. 3D System Integration, 7-9, San Francisco, Sep. 2009.

5. Xu, C., H. Li, R. Suaya, and K. Banerjee, "Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs," IEEE Trans. Electron Devices, Vol. 57, No. 12, 3405-3417, Dec. 2010.
doi:10.1109/TED.2010.2076382

6. Pak, J. S., J. Cho, J. Kim, J. Lee, H. Lee, K. Park, and J. H. Kim, Slow wave and dielectric quasi-TEM modes of metal-insulator-semiconductor (MIS) structure through silicon via (TSV) in signal propagation and power delivery in 3D chip package, IEEE Electronic Compon. Tech. Conf., 667-672, Las Vegas, Jun. 2010.

7. Han, K. J., M. Swaminathan, and T. Bandyopadhyay, "Electromagnetic modeling of through-silicon vias (TSV) interconnections using cylindrical modal basis functions," IEEE Trans. Adv. Packag., Vol. 33, No. 4, 804-817, Nov. 2010.
doi:10.1109/TADVP.2010.2050769

8. Katti, G., M. Stucchi, J. V. Olmen, K. D. Meyer, and W. Dehaene, "Through-silicon-via capacitance reduction technique to benefit 3-D IC performance," IEEE Electron Device Lett., Vol. 31, No. 4, 549-551, Jun. 2010.
doi:10.1109/LED.2010.2046712

9. Katti, G., et al., Temperature dependent electrical characteristics of through-Si-via (TSV) interconnections, 2010 IEEE Int. Interconnect Tech. Conf., 7-9, Jun. 2010.

10. Selvanayagam, C. S., J. H. Lau, X. Zhang, S. Seah, V. Vaidyanathan, and T. C. Chai, "Nonlinear thermal stress/strain analysis of copper filled TSV (through silicon via) and their flip-chip microbumps," IEEE Trans. Adv. Packag., Vol. 32, No. 4, 720-728, Oct. 2009.
doi:10.1109/TADVP.2009.2021661

11. Wang, X. P., W. Y. Yin, and S. He, "Multiphysics characterization of transient electrothermomechanical responses of through-silicon vias applied with a periodic voltage pulse," IEEE Trans. Electron. Devices, Vol. 57, No. 6, 1382-1389, Jun. 2010.
doi:10.1109/TED.2010.2045676

12. Tyagi, M. S., Introduction to Semiconductor Materials and Devices, New York, Wiley, 1991.

13. Yin, W. Y., K. Kang, and J. F. Mao, "Electromagnetic-thermal characterization of on-chip coupled (a)symmetrical interconnects," IEEE Trans. Adv. Packag., Vol. 30, No. 4, 851-863, Nov. 2007.
doi:10.1109/TADVP.2007.908016

14. Shi, X., K. S. Yeo, W. M. Lim, M. A. Do, and C. C. Boon, "A spice compatible model of on-wafer coupled interconnects for CMOS RFICs," Progress In Electromagnetics Research, Vol. 102, 287-299, 2010.
doi:10.2528/PIER10010608

15. Babic, S. I., F. Sirois, and C. Akyel, "Validity check of mutual inductance formulas for circular filaments with lateral and angular misalignments," Progress In Electromagnetics Research M, Vol. 8, 15-26, 2009.
doi:10.2528/PIERM09060105

16. Carretero, C., R. Alonso, J. Acero, and J. M. Burdio, "Coupling impedance between planar coils inside a layered media," Progress In Electromagnetics Research, Vol. 112, 381-396, 2011.

17. Xie, H., J. Wang, R. Fan, and Y. Liu, "Study of loss effect of transmission lines and validity of a spice model in electromagnetic topology," Progress In Electromagnetics Research, Vol. 90, 89-103, 2009.
doi:10.2528/PIER08121605

18. Kang, Y., H. Kim, J. Lee, Y. Son, B. G. Park, J. D. Lee, and H. Shin, "Modeling of polysilicon depletion effect in recessed-channel MOSFETs," IEEE Electron Device Lett., Vol. 30, No. 2, 1371-1373, Feb. 2009.
doi:10.1109/LED.2009.2034278

19. Yang, K., W. Y. Yin, J. Shi, K. Kang, J. F. Mao, and Y. P. Zhang, "A study of on-chip spiral inductors," IEEE Trans. Electron. Devices, Vol. 55, No. 11, 3236-3245, Nov. 2008.
doi:10.1109/TED.2008.2004648

20. Mustafa, F. and A. M. Hashim, "Properties of electromagnetic fields and effective permittivity excited by drifting plasma waves in semiconductor-insulator interface structure and equivalent transmission line technique for multi-layered structure," Progress In Electromagnetics Research, Vol. 104, 403-425, 2010.
doi:10.2528/PIER10041504

21. Eudes, T., B. Ravelo, and A. Louis, "Transient response characterization of the high-speed interconnection RLCG-model for the signal integrity analysis," Progress In Electromagnetics Research, Vol. 112, 183-197, 2011.

22. Khalaj-Amirhosseini, M., "Closed form solutions for nonuniform transmission lines," Progress In Electromagnetics Research B, Vol. 2, 243-258, 2008.
doi:10.2528/PIERB07111502

23. Kaiser, K. L., Electromagnetic Compatibility Handbook, CRC Press, Boca Raton, 2005.

24. Bedrosian, G., "High-performance computing for finite element methods in low-frequency electromagnetics," Progress In Electromagnetics Research, Vol. 7, 57-110, 1993.

25. Hellicar, A. D., J. S. Kot, G. C. James, and G. K. Cambrell, "The analysis of 3D model characterization and its impact on the accuracy of scattering calculations," Progress In Electromagnetics Research, Vol. 110, 125-145, 2010.
doi:10.2528/PIER10092703


© Copyright 2014 EMW Publishing. All Rights Reserved