PIER C
 
Progress In Electromagnetics Research C
ISSN: 1937-8718
Home | Search | Notification | Authors | Submission | PIERS Home | EM Academy
Home > Vol. 74 > pp. 31-40

4-BIT KA BAND SIGE BICMOS DIGITAL STEP ATTENUATOR

By M. M. Sarfraz, Y. Liu, F. Ullah, M. Wang, Z.-Q. Li, and H. Zhang

Full Article PDF (2,945 KB)

Abstract:
This paper presents a Ka-band 4-bit BiCMOS digital step attenuator with maximum attenuation of 7.5 dB (16 states). The proposed attenuator design is based on switched T-bridge network including phase correction network and is fabricated in 0.13 μm SiGe BiCMOS technology. Attenuator with phase correction structure shows root mean square (RMS) amplitude errors <0.8 dB at 31 to 33 GHz and the RMS insertion phase varying from 2.8° to 5.8° over 31-33 GHz. The measured insertion loss is 19 dB and total chip size including pad is 1.92×0.4 mm2.

Citation:
M. M. Sarfraz, Y. Liu, F. Ullah, M. Wang, Z.-Q. Li, and H. Zhang, "4-Bit Ka Band SiGe BiCMOS Digital Step Attenuator," Progress In Electromagnetics Research C, Vol. 74, 31-40, 2017.
doi:10.2528/PIERC17030802

References:
1. Ku, B. H. and S. Hong, "6-bit CMOS digital attenuators with low phase variations for X-band phased-array systems," IEEE Transactions on Microwave Theory and Techniques, Vol. 58, No. 7, 1651-1663, 2010.
doi:10.1109/TMTT.2010.2049691

2. Sun, P., "Analysis of phase variation of CMOS digital attenuator," Electronics Letters, Vol. 50, No. 25, 1912-1914, 2014.
doi:10.1049/el.2014.2640

3. Goyal, U. and A. Kumar, Design and Development of an S-band 6 bit MMIC Attenuator with Low Insertion Loss, 157-159, 2014.

4. Ciccognani, W., et al., "Compensating digital attenuator differential phase shift," 2008 14th Conference on Microwave Techniques, 2008.

5. Hajimiri, A., "mm-wave silicon ICs: Challenges and opportunities," 2007 IEEE Custom Integrated Circuits Conference, 2007.

6. Dogan, H., R. G. Meyer, and A. M. Niknejad, "Analysis and design of RF CMOS attenuators," IEEE Journal of Solid-State Circuits, Vol. 43, No. 10, 2269-2283, 2008.
doi:10.1109/JSSC.2008.2004325

7. Sjogren, L., et al., "A low phase-error 44-GHz HEMT attenuator," IEEE Microwave and Guided Wave Letters, Vol. 8, No. 5, 194-195, 1998.
doi:10.1109/75.668708

8. Hunton, J. K. and A. G. Ryals, "Microwave variable attenuators and modulators using PIN diodes," IRE Transactions on Microwave Theory and Techniques, Vol. 10, No. 4, 262-273, 1962.
doi:10.1109/TMTT.1962.1125506

9. Min, B. W. and G. M. Rebeiz, "A 10-50-GHz CMOS distributed step attenuator with low loss and low phase imbalance," IEEE Journal of Solid-State Circuits, Vol. 42, No. 11, 2547-2554, 2007.
doi:10.1109/JSSC.2007.907205

10. Bae, J., J. Lee, and C. Ngyyen, "A 10-67-GHz CMOS dual-function switching attenuator with improved ," IEEE Transactions on Microwave Theory and Techniques, Vol. 61, No. 12, 4118-4129, 2013.
doi:10.1109/TMTT.2013.2288694

11. Razavi, B., Design of Analog CMOS Circuit Design, 2nd Ed., Oxfard University Press, New York, 2004.

12. Zhang, Y., et al., "A 5-bit lumped 0.18-μm CMOS step attenuator with low insertion loss and low phase distortion in 3{22 GHz applications," Microelectronics Journal, Vol. 45, No. 4, 468-476, 2014.
doi:10.1016/j.mejo.2014.02.013

13. Kaunisto, R., et al., "A linear-control wide-band CMOS attenuator," ISCAS 2001, The 2001 IEEE International Symposium on Circuits and Systems (Cat. No. 01CH37196), 2001.

14. Ju, I., Y. S. Noh, and I. B. Yom, "Ultra broadband DC to 40 GHz 5-bit pHEMT MMIC digital attenuator," European Microwave Conference, Vol. 2, 4, 2005.

15. Kang, D.-W., et al., "Ku-band MMIC phase shifter using a parallel resonator with 0.18-μm CMOS technology," IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 1, 294-301, 2006.
doi:10.1109/TMTT.2005.860298

16. Davulcu, M., et al., "7-bit SiGe-BiCMOS step attenuator for X-band phased-array RADAR applications," IEEE Microwave and Wireless Components Letters, Vol. 26, No. 8, 598-600, 2016.
doi:10.1109/LMWC.2016.2585565


© Copyright 2010 EMW Publishing. All Rights Reserved