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2009-03-20

A 802.11a Pulse-Swallow Integer-n Frequency Synthesizer

By Cheng-Chan Tien, Tsung-Mo Tien, and Christina F. Jou
Progress In Electromagnetics Research C, Vol. 7, 25-35, 2009
doi:10.2528/PIERC09021705

Abstract

In this paper we will explain thoroughly a 802.11a pulse-swallow integer-N frequency synthesizer. The whole circuit is designed on chip except the loop filter. The reference frequency is set to 10 MHz and a pulse-swallow counter is designed for the purpose of controlling the dual-modulus divider (÷8/9). The frequency tuning range varies from 4.98 GHz to 5.73 GHz meanwhile the output power of the voltage-controlled oscillator is -13.5 dBm, and the phase noise measured at 1MHz is -126 dBc/Hz. The settling time of the closed loop is about 20 us, the total power dissipation is 26.35 mW with 1.8 V supply voltage. The chip is fabricated under TSMC CMOS 0.18 um.

Citation


Cheng-Chan Tien, Tsung-Mo Tien, and Christina F. Jou, "A 802.11a Pulse-Swallow Integer-n Frequency Synthesizer," Progress In Electromagnetics Research C, Vol. 7, 25-35, 2009.
doi:10.2528/PIERC09021705
http://www.jpier.org/PIERC/pier.php?paper=09021705

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