Progress In Electromagnetics Research
ISSN: 1070-4698, E-ISSN: 1559-8985
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By W.-T. Huang, C.-H. Lu, and D.-B. Lin

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The reliability of circuits on printed circuit boards (PCBs) in many modern electronic products is affected by severe noise caused by high-speed and low-voltage operation as well as layout constraints compounded by limited space and high circuit density. Crosstalk is a major noise source that interferes with the signal integrity (SI) in poor PCB layout designs. One common method of reducing crosstalk is the three-width (3-W) rule. The serpentine guard trace (SGT) approach has also been used to reduce crosstalk using two terminal matching resistors on the SGT between the aggressor and victim. Although the SGT approach suppresses far-end crosstalk (FEXT) at the expense of more layout space, it also neglects interference caused by near-end crosstalk (NEXT). In this study, we propose the SGT via (SGTV) approach in which grounded vias are added to the SGT at appropriate locations, and the ratio between the lengths of the horizontal and vertical sections of the guard trace is adjusted to minimize NEXT and FEXT. Frequency domain simulated (measured) results showed that the SGTV approach reduced NEXT by 3.7 (7.65) and 0.83 (1.6) dB as well as FEXT by 5.11 (7.22) and 0.1 (1.98) dB compared to the 3-W and SGT approaches, respectively. In the time domain, simulated (measured) results showed that SGTV reduced NEXT by 34.67% (49.8%) and 27.5% (26.65%) as well as FEXT by 46.78% (56.52%) and 6.91% (24.8%) compared to the 3-W and SGT approaches, respectively. Our proposed approach thus effectively suppresses both NEXT and FEXT to achieve better SI in PCB layout designs than the other two methods. As our design uses two grounded vias instead of two guard trace terminators and does not require extra components, it is less costly than SGT. Our simulated and measured results indicate that our approach is suitable for practical application because of the lower cost and the ease of implementation that eliminates NEXT and FEXT.

W.-T. Huang, C.-H. Lu, and D.-B. Lin, "Suppression of Crosstalk Using Serpentine Guard Trace Vias," Progress In Electromagnetics Research, Vol. 109, 37-61, 2010.

1. Sharawi, M. S., "Practical issues in high speed PCB design," IEEE Potentials, Vol. 23, No. 2, 24-27, Apr.-May 2004.

2. Kim, J., H. Lee, and J. Kim, "Effects on signal integrity and radiated emission by split reference plane on high-speed multilayer printed circuit boards," IEEE Transactions on Advanced Packaging, Vol. 28, No. 4, 724-735, Nov. 2005.

3. Lee, K., H. B. Lee, H. K. Jung, J. Y. Sim, and H. J. Park, "A serpentine guard trace to reduce the far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines," IEEE Transactions on Advanced Packaging, Vol. 31, No. 4, 809-817, Nov. 2008.

4. Lee, K., H. K. Jung, H. J. Chi, H. J. Kwon, J. Y. Sim, and H. J. Park, "Serpentine microstrip line with zero far-end crosstalk for parallel high-speed DRAM interfaces," IEEE Transactions on Advanced Packaging, Vol. 33, No. 2, 552-558, May 2010.

5. Jarvis, B. D., "The effects of interconnections on high-speed logic circuits," IEEE Transactions on Electronic Computers, Vol. 12, No. 5, 476-487, Oct. 1963.

6. Feller, A., H. R. Kaupp, and J. J. Digiacomo, "Crosstalk and reflections in high-speed digital systems," Fall Joint Computer Conference, 511-525, Las Vegas, NV, Nov. 1965.

7. Sohn, Y. S., J. C. Lee, H. J. Park, and S. I. Cho, "Empirical equations on electrical parameters of coupled microstrip lines for crosstalk estimation in printed circuit board," IEEE Transactions on Advanced Packaging, Vol. 24, No. 4, 521-527, Nov. 2001.

8. Chen, H. and Y. Zhang, "A synthetic design of eliminating crosstalk within MTLS," Progress In Electromagnetics Research, Vol. 76, 211-221, 2007.

9. Xiao, F., R. Hashimoto, K. Murano, and Y. Kami, "Analysis of crosstalk between single-ended and differential lines," PIERS Online, Vol. 3, No. 1, 2007.

10. Kayama, S., M. Sonehara, T. Sato, K. Yamasawa, and Y. Miura, "Cross-talk suppression in high-density printed circuit boards using magnetic composite filled in spacing between signal lines," IEEE Transactions on Magnetics, Vol. 45, No. 10, 4801-4803, Oct. 2009.

11. Bogatin, E., Signal Integrity-simplified, Prentice Hall, 2003.

12. Hall, S. H. and H. L. Heck, Advanced Signal Integrity for High-speed Digital System Design, Wiley, Hoboken, NJ, 2009.

13. Montrose, M. I., EMC and the Printed Circuit Board: Design, Theory, and Layout Made Simple, IEEE Press, 1998.

14. Chilo, J. and T. Arnaud, "Coupling effects in the time domain for an interconnecting bus in high-speed GaAs logic circuits," IEEE Transactions Electron Devices, Vol. 32, No. 3, 347-352, Mar. 1984.

15. You, H. and M. Soma, "Crosstalk analysis of interconnection lines and packages in high-speed integrated circuits," IEEE Transactions on Circuits and Systems, Vol. 37, No. 8, 1019-1026, Aug. 1990.

16. Novak, I., B. Eged, and L. Hatvani, "Measurement and simulation of crosstalk reduction by discrete discontinuities along coupled PCB traces," IEEE Transactions on Instrumentation and Measurement, Vol. 43, No. 2, 170-175, Apr. 1994.

17. Sharma, R., T. Chakravarty, and A. B. Bhattacharyya, "Transient analysis of microstrip-like interconnections guarded by ground tracks," Progress In Electromagnetics Research, Vol. 82, 189-202, 2008.

18. Ladd, D. N. and G. I. Costache, "SPICE simulation used to characterize the crosstalk reduction effect of additional tracks grounded with vias on printed circuit boards," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processibg, Vol. 39, No. 6, 342-347, Jun. 1992.

19. Cheng, Y. S., W. D. Guo, C. P. Hung, R. B.Wu, and D. de Zutter, "Enhanced microstrip guard trace for ringing noise suppression using a dielectric superstrate," IEEE Transactions on Advanced Packaging, IEEE Early Access, 2010.

20. Huang, W. T., C. H. Lu, and D. B. Lin, "Design of suppressing crosstalk by vias of serpentine guard trace," PIERS Proceedings, 484-488, Xian, China, Mar. 22-26, 2010.

21. Mallahzadeh, A. R., A. H. Ghasemi, S. Akhlaghi, B. Rahmati, and R. Bayderkhani, "Crosstalk reduction using step shaped transmission line," Progress In Electromagnetics Research C, Vol. 12, 139-148, 2010.

22. Young, B., Digital Signal Integrity: Modeling and Simulations with Interconnects and Packages, Prentice-Hall, 2001.

23. Lee, S. K., K. Lee, H. J. Park, and J. Y. Sim, "FEXT-eliminated stub-alternated microstrip line for multi-gigabit/second parallel links," Electronics Letters, Vol. 44, No. 4, 272-273, Feb. 2008.

24. Suntives, A., A. Khajooeizadeh, and R. Abhari, "Using via fences for crosstalk reduction in PCB circuits," IEEE International Symposium on Electromagnetic Compatibility, Vol. 1, 34-37, Aug. 2006.

25. Huang, W. T., C. H. Lu, and D. B. Lin, "The optimal number and location of grounded vias to reduce crosstalk," Progress In Electromagnetics Research, Vol. 95, 241-266, 2009.

26. Rodriguez-Cepeda, P., M. Ribó, F. J. Pajares, J. R. Regué, A. M. Sánchez, and A. Pérez, "Multimodal analysis of guard traces," IEEE International Symposium on Electromagnetic Compatibility, 1-5, Honolulu, HI, Jul. 2007.

27. Mbairi, F. D., W. P Siebert, and H. Hesselbom, "On the problem of using guard traces for high frequency differential lines crosstalk reduction," IEEE Transactions on Components and Packaging Technologies, Vol. 30, No. 1, 67-74, Mar. 2007.

28. IE3D User's Manual, Zeland Software, Inc, 2000.

29. Novak, I., B. Eged, and L. Hatvani, "Measurement by vector-network analyzer and simulation of crosstalk reduction on printed board with additional center traces," IEEE Institute of Technology Conference, 269-274, Irvine, CA, 1993.

30. Hua, R. C., C. F. Chou, S. J. Wu, and T. G. Ma, "Compact multiband planar monopole antennas for smart phone applications," IET Microwaves, Antennas & Propagation, Vol. 2, No. 5, 473-481, Aug. 2008.

31. Schneider, M. V., "Microstrip lines for microwave integrated circuits," Bell System Tech. Jn., Vol. 48, 1422-1444, 1969.

32. Wu, T. L., Y. H. Lin, T. K. Wang, C. C. Wang, and S. T. Chen, "Electromagnetic bandgap power/ground planes for wideband suppression of ground bounce noise and radiated emission in high-speed circuits," IEEE Transactions on Microwave Theory and Techniques, Vol. 53, No. 9, 2935-2942, Sep. 2005.

33. Hall, S. H., G. W. Hall, and J. A. McCall, High-speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, John-Wiley & Sons, 2000.

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