Reflective interference caused by impedance discontinuities in the interconnect is a serious impediment to high speed serial link designs. The reflections can be addressed either through expensive equalization circuits or through interconnect redesign. Here a new technique for determining the most significant places to make changes in an interconnect design is presented. Through linearizing the S-parameter cascading process three unique reflection budgets are created based on 1) frequency domain insertion loss deviation, 2) time domain peak distortion analysis and 3) time domain reflectometry. Example analysis of a 25.8 Gb/s NRZ system identifies the connectors as the primary contributors to reflective interference and estimates that the interactions with the rest of the interconnect with the connector impedance discontinuities reduces the system eye height by 84 mV.
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