volume | PIER Journals

Abstract

In this paper, a novel broadband equalizer optimization technique is introduced for high-speed digital system designs. Through effectively compensating both conductor loss and dielectric loss, this technique provides a new solution to find optimal equalizer for high-speed signaling over printed circuit board (PCB) with continuous time linear equalizer (CTLE) as an application. The coefficients of CTLE are quickly identified through searching the minimum of the variation of total transfer functions over the low-mid frequency range. Channel simulations with different server interfaces of 12 Gbps and 25 Gbps are performed, respectively. Simulation results are presented to validate the technique.

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Dr. Shaowu Huang

Dr. Beomtaek Lee