volume | PIER Journals

Abstract

An accurate and behavioral modeling method of symmetrical T-tree interconnect network is successfully investigated in this paper. The T-tree network topology understudy is consisted of elementary lumped L-cells formed by series impedance and parallel admittance. It is demonstrated how the input-output signal paths of this single input multiple output (SIMO) tree network can be reduced to single input single output (SISO) network composed of L-cells in cascade. The literal expressions of the currents, the input impedances and the voltage transfer function of the T-tree electrical interconnect via elementary transfer matrix products are determined. Thus, the exact expression of the multi-level behavioral T-tree transfer function is established. The routine algorithm developed was implemented in Matlab programs. As application of the developed modeling method, the analysis of T-tree topology comprised of different and identical RLC-cells is conducted. To demonstrate the relevance of the model established, lumped RLC T-tree networks with different levels for the microelectronic interconnect application are designed and simulated. The work flow illustrating the guideline for the application of the routine algorithm summarizing the modeling method is proposed. Then, 3D-microstrip T-tree interconnects with width 0.1 μm and length 3 mm printed on FR4-substrate were considered. As results, very good agreement between the results from the reduced behavioral model proposed and SPICE-computations is found both in frequency- and time-domains by considering arbitrary binary sequence ''01001100" with 2 Gsym/s rate. The model proposed in this paper presents significant benefits in terms of flexibility and very less computation times. It can be used during the design process of the PCB and the microelectronic circuits for the signal integrity prediction. In the continuation of this work, the modeling of clock T-tree interconnects for packaging systems composed of distributed elements using an analogue process is in progress.

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Prof. Blaise Ravelo