volume | PIER Journals

Abstract

This paper presents a comprehensive analysis of a current-mode-logic frequency divider (CML FD) and the theoretical locking range of CML FD. The locking range of the CML divider is proportional to the injection ratio. By adding a resistive load, the locking range of the CML divider is not limited by the Q value of the LC resonant circuit. The minimum input power to drive the divider is achieved when the output frequency is equal to the self-oscillation frequency. To verify the properties of wideband and multi-phase outputs, the ÷4 octet-phase frequency divider based on a two-stage CML FD was implemented using a 0.18 μm CMOS process. It has a locking range of 1 GHz to 8 GHz with a 12.6 mW dc power consumption, and the phase deviation between the octet output signals is less than 4.7°. With an ultra-wide frequency bandwidth and accurate octet outputs, the proposed divider is suitable for multi-phase generator applications.

1. Mazzanti, A., M. Sosio, M. Repossi, and F. Svelto, "A 24 GHz subharmonic direct conversion receiver in 65 nm CMOS," IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 58, No. 1, 88-97, 2011.
doi:10.1109/TCSI.2010.2071711 Google Scholar

2. Kim, S. and L. E. Larson, "A 44-GHz SiGeBiCMOS phase-shifting sub-harmonics up-converter for phase-array transmitters," IEEE Trans. Microw. Theory Tech., Vol. 58, No. 5, 1089-1099, 2010.
doi:10.1109/TMTT.2010.2045567 Google Scholar

3. Mazzanti, A., P. Uggetti, and F. Svelto, "Analysis and design of injection-locked LC dividers for quadrature generation," IEEE J. Solid-State Circuits, Vol. 39, No. 9, 1425-1433, 2004.
doi:10.1109/JSSC.2004.831596 Google Scholar

4. Alioto, M. and G. Palumbo, "Power-aware design techniques for nanometer MOS current-mode logic gates: A design framework," IEEE Circuits and System Magazine, 42-61, Fourth quarter, 2006. Google Scholar

5. Alioto, M., R. Mita, and G. Palumbo, "Design of high-speed power-efficient MOS current-mode logic frequency dividers," IEEE Trans. Circuits Syst. II, Vol. 53, No. 11, 1165-1169, 2006.
doi:10.1109/TCSII.2006.882350 Google Scholar

6. Zhou, C., L. Zang, L. Zhang, Z. Yu, and H. Qian, "Injection-locking-based power and speed optimization of CML dividers," IEEE Trans. Circuits Syst. II, Vol. 58, No. 9, 565-569, 2011.
doi:10.1109/TCSII.2011.2161163 Google Scholar

7. Jang, S. L., T. C. Kung, and C. W. Hsue, "Wide-locking range divide-by-4 injection-locked frequency divider using linear mixer approach," IEEE Microw. Wireless Compon. Lett., Vol. 27, No. 4, 398400, 2017.
doi:10.1109/LMWC.2017.2678441 Google Scholar

8. Lee, S. H., S. L. Jang, and Y. H. Chung, "A low voltage divide-by-4 injection-locked frequency divider with quadrature outputs," IEEE Microw. Wireless Compon. Lett., Vol. 17, No. 5, 373-375, 2007.
doi:10.1109/LMWC.2007.895718 Google Scholar

9. Singh, U. and M. M. Green, "High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz," IEEE J. Solid-State Circuits, Vol. 40, No. 8, 1658-1661, 2005.
doi:10.1109/JSSC.2005.852420 Google Scholar

10. Cheema, H. H., R. Mahmoudi, M. A. T. Sandulean, and A. van Roermund, "A Ka band, static, MCML frequency divider in standard 90-nm-CMOS LP for 60 GHz applications," Proc. IEEE Radio Frequency Integrated Circuits Symp., 541-544, 2007. Google Scholar

11. Jang, S. L. and C. C. Fu, "Wide locking range divide-by-4 LC-tank injection-locked frequency divider using series-mixers," Analog Integr. Circuits Signal Process., Vol. 78, No. 2, 523-528, 2014.
doi:10.1007/s10470-013-0171-2 Google Scholar

Dr. Si-Da Tang

Dr. Yu-Sheng Lin

Dr. Wei-Hsiang Huang

Dr. Chun-Lin Lu

Prof. Yeong-Her Wang