volume | PIER Journals

2009-03-20

A 802.11a Pulse-Swallow Integer-n Frequency Synthesizer

Cheng-Chan Tien,

Mr. Cheng-Chan Tien

National Chiao-Tung University

Taiwan, China

Homepage

Tsung-Mo Tien,

Dr. Tsung-Mo Tien

Department of Hydraulic and Ocean Engin

National Cheng Kung University

Taiwan

Homepage

Christina F. Jou

Dr. Christina F. Jou

Institute of Communication Engineering

National Chiao-Tung University

Taiwan

Homepage

Progress In Electromagnetics Research C, Vol. 7, 25-35, 2009

doi:10.2528/PIERC09021705

Abstract

In this paper we will explain thoroughly a 802.11a pulse-swallow integer-N frequency synthesizer. The whole circuit is designed on chip except the loop filter. The reference frequency is set to 10 MHz and a pulse-swallow counter is designed for the purpose of controlling the dual-modulus divider (÷8/9). The frequency tuning range varies from 4.98 GHz to 5.73 GHz meanwhile the output power of the voltage-controlled oscillator is -13.5 dBm, and the phase noise measured at 1MHz is -126 dBc/Hz. The settling time of the closed loop is about 20 us, the total power dissipation is 26.35 mW with 1.8 V supply voltage. The chip is fabricated under TSMC CMOS 0.18 um.

Citation

Copy Export

Cheng-Chan Tien, Tsung-Mo Tien, and Christina F. Jou, "A 802.11a Pulse-Swallow Integer-n Frequency Synthesizer," Progress In Electromagnetics Research C, Vol. 7, 25-35, 2009.
doi:10.2528/PIERC09021705

References

1. Shen, W., K. Hu, X. Yi, Y. Zhou, and Z. Hong, "A 5GHz CMOS monolithic fractional-N frequency synthesizer," 6th International Conference on ASIC 2005, ASICON 2005, Vol. 2, 624-627, Oct. 24-27, 2005.
doi:10.1109/ICASIC.2005.1611406

2. Leung, L. L. K. and H. C. Luong, "A 1-V, 9.7mW CMOS frequency synthesizer for WLAN 802.11a transceivers," 2005 Symposium on VLSI Circuits, 2005. Digest of Technical Papers, 252-255, June 16-18, 2005, Digital Object Identifier 10.1109/VLSIC.2005.1469379.

3. Herzel, F., G. Fischer, and H. Gustat, "An integrated CMOS RF synthesizer for 802.11a wireless LAN," IEEE Journal of Solid-state Circuits, Vol. 38, No. 10, 1767-1770, Oct. 2003, Digital Object Identifier 10.1109/JSSC.2003.817601.
doi:10.1109/JSSC.2003.817601

4. Theill, D., C. Durdodt, A. Hanke, S. Heinen, S. van Waasen, D. Seippel, D. Pham-Stabner, and K. Schumacher, "A fully integrated CMOS frequency synthesizer for bluetooth," IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 103-106, Phoenix, Arizona, USA, May 20-22, 2001.

5. Foroudi, N. and T. A. Kwasniewski, "CMOS high-speed dual-modulus frequency divider for RF frequency synthesis," IEEE Journal of Solid-state Circuits, Vol. 30, No. 2, 93-100, Feb. 1995, Digital Object Identifier 10.1109/4.341735.
doi:10.1109/4.341735

6. Sulaiman, M. S. and N. Khan, "A novel low-power high-speed programmable dual modulus divider for PLL-based frequency synthesizer ," Proceedings of IEEE International Conference on Semiconductor Electronics, 2002, ICSE 2002, 77-81, Dec. 19-21, 2002, Digital Object Identifier 10.1109/SMELEC.2002.1217779.