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2018-07-30
Chip-Package Co-Design for Optimization of 5.8 GHz LNA Performance Based on Embedded Inductors
By
Progress In Electromagnetics Research M, Vol. 71, 95-105, 2018
Abstract
This paper presents the design and demonstration of an optimized land grid array (LGA) structure for low noise amplifier (LNA). In order to achieve better circuit performance, the novel chip-package co-design method based on embedded inductors is used. The optimized structure is accurately modeled by ANSYS software. S-parameter is utilized to help in understanding the contributing to the optimized LGA structure. The simulation results for the novel LNA co-design structure show the gain 14.35 dB (> 10 dB), input reflection coefficient -15.63 dB (< -10 dB), output reflection coefficient -24.43 dB (< -10 dB), reverse-isolation -44.7 dB (< -20 dB), and noise figure 2.99 dB (< 4 dB), and indicate that the optimized LGA structure based on embedded inductors is fully capable of supporting 5.8 GHz LNA application.
Citation
Haiyan Sun Wenjun Sun Ling Sun Jicong Zhao Yihong Peng Jiaen Fang Xiaoyong Miao Honghui Wang , "Chip-Package Co-Design for Optimization of 5.8 GHz LNA Performance Based on Embedded Inductors," Progress In Electromagnetics Research M, Vol. 71, 95-105, 2018.
doi:10.2528/PIERM18051403
http://www.jpier.org/PIERM/pier.php?paper=18051403
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