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2010-10-29
Linearity Improvement of Cascode CMOS LNA Using a Diode Connected Nmos Transistor with a Parallel RC Circuit
By
Progress In Electromagnetics Research C, Vol. 17, 29-38, 2010
Abstract
A fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) using post-linearization technique, implemented in a 0.18 μm RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise figure (NF) and power consumption. The LNA achieves an input third-order intercept point (IIP3) of +8.33 dBm, a power gain of 10.02 dB, and a NF of 3.05 dB at 5.5 GHz biased at 6 mA from a 1.8 V power supply.
Citation
Chieh-Pin Chang Wei-Chih Chien Chun-Chi Su Yeong-Her Wang Ja-Hao Chen , "Linearity Improvement of Cascode CMOS LNA Using a Diode Connected Nmos Transistor with a Parallel RC Circuit," Progress In Electromagnetics Research C, Vol. 17, 29-38, 2010.
doi:10.2528/PIERC10082411
http://www.jpier.org/PIERC/pier.php?paper=10082411
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