volume | PIER Journals

Abstract

This paper gives a comprehensive study on the modeling and design challenges of Through Silicon Vias (TSVs) in high speed three dimensional (3D) system integration. To investigate the propagation characteristics incurred by operations within the ultra-broad band frequency range, we propose an equivalent circuit model which accounts for rough sidewall effect and high frequency effect. A closed-form expression for TSV metal oxide semiconductor (MOS) capacitance in both depletion and accumulation regions is proposed. The coupling of TSV arrays and near and far field effect on crosstalk analysis are performed using 3D EM field solver. Based on the TSV circuit model, we optimize the TSVs' architecture and manufacturing process parameters and develop effective design guidelines for TSVs which could be used to resolve the signal integrity issues arising at high frequency data transmission in 3D ICs.

1. Che, F. X., W. N. Putra, A. Heryanto, A. Trigg, S. Gao, and C. L. Gan, "Numerical and experimental study on Cu protrusion of Cu-filled through-silicon vias (TSV)," Proc. IEEE Int. 3DIC Conf., 1-6, 2012. Google Scholar

2. Swaminathan, M., "Electrical design and modeling challenges for 3D system integration," Design Conference 2012, 2012. Google Scholar

3. Banerjee, K., S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE, Vol. 89, No. 5, 602-633, 2001.
doi:10.1109/5.929647 Google Scholar

4. Koyanagi, M., H. Kurino, K.-W. Lee, K. Sakuma, N. Miyakawa, and H. Itani, "Future system-on-silicon LSI chips," IEEE Micro., Vol. 18, No. 4, 17-22, 1998.
doi:10.1109/40.710867 Google Scholar

5. Zhang, L., H. Y. Li, S. Gao, and C. S. Tan, "Achieving stable Through-Silicon Via (TSV) capacitance with oxide fixed charge," IEEE Elect. Device Lett., Vol. 32, No. 5, 668-670, 2011.
doi:10.1109/LED.2011.2111351 Google Scholar

6. Salah, K., H. Ragai, Y. Ismail, and A. E. Rouby, "Equivalent lumped element models for various n-port Through Silicon Vias networks," Proc. 16th ASP-DAC, 176-183, 2011. Google Scholar

7. Ehsan, M. A., Z. Zhou, and Y. Yi, "Electrical modeling and analysis of sidewall roughness of Through Silicon Vias in 3D integration," Proc. IEEE Int. Conf. EMC, 52-56, Aug. 2014. Google Scholar

8. Bandyopadhyay, T., R. Chatterjee, D. Chung, M. Swaminathan, and R. Tummala, "Electrical modeling of Through Silicon and Package Vias," Proc. IEEE Int. Conf. 3D Syst. Integr., 1-8, Sep. 2009. Google Scholar

9. ITU-D "Measuring the information society 2011," International Telecommunications Union (ITU), 2011. Google Scholar

10. Federal Communications Commission (FCC) "National broadband plan,", http://www.broadband.gov-/plan/executive-summary/, 2011. Google Scholar

11. Pi, Z. and F. Khan, "An introduction to millimeter-wave mobile broadband systems," IEEE Communications Magazine, Vol. 49, No. 6, 101-107, 2011.
doi:10.1109/MCOM.2011.5783993 Google Scholar

12. Liu, D., U. Pfeiffer, J. Gryzb, and B. Gaucher, Advanced Millimeter Wave Technologies: Antennas, Packaging, and Circuits, J. Wiley & Sons, 2009.
doi:10.1002/9780470742969

13. Oprysko, M., "Building millimeter-wave circuits in silicon," Proc. IEEE Radio and Wireless Conf. on Adv. in RF and High Speed Syst. Integr., 2004. Google Scholar

14. Nakamura, T., H. Kitada, Y. Mizushima, N. Maeda, K. Fujimoto, and T. Ohba, "Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects," Proc. IEEE Int. Conf. 3D Syst. Integr., 1-4, Jan./Feb. 2012. Google Scholar

15. Ndip, I., B. Curran, K. Lobbicke, S. Guttowski, H. Reichl, K. Lang, and H. Henke, "High-frequency modeling of TSVs for 3-D chip integration and silicon interposers considering skin-effect, dielectric quasi-TEM and slow-wave modes," IEEE Trans. Compon. Packag. Manuf. Technol., Vol. 1, No. 10, 1627-1641, Oct. 2011.
doi:10.1109/TCPMT.2011.2164915 Google Scholar

16. Yi, Y. and Y. Zhou, "Differential Through-Silicon-Vias modeling and design optimization to benefit 3D IC performance," Proc. IEEE 22nd Conf. EPEPS, 195-198, Oct. 2013. Google Scholar

17. Yi, Y. and Y. Zhou, "A novel circuit model for multiple Through-Silicon-Vias (TSVs)," Proc. IEEE Int. Conf. 3DIC, 1-4, Sep. 2013. Google Scholar

18. Yi, Y., Y. Zhou, X. Fu, and F. Shen, "Modeling differential Through-Silicon-Vias (TSVs) with voltage dependent and nonlinear capacitance," J. of Selectd. Area. Microelect., Vol. 3, No. 6, 27-36, Jun. 2013. Google Scholar

19. Xu, C., H. Li, R. Suaya, and K. Banerjee, "Compact AC modeling and performance analysis of Through-Silicon Vias in 3-D ICs," IEEE Trans. Electron Devices, Vol. 57, No. 12, 3405-3417, 2010.
doi:10.1109/TED.2010.2076382 Google Scholar

20. Engin, A. E. and S. R. Narasimhan, "Modeling of crosstalk in Through Silicon Vias," IEEE Trans. Electromagn. Compatibil., Vol. 55, No. 1, 149-158, Feb. 2013.
doi:10.1109/TEMC.2012.2206816 Google Scholar

21. Xie, B., M. Swaminathan, K. J. Han, and J. Xie, "Coupling analysis of Through-Silicon Via (TSV) arrays in silicon interposers for 3D systems," Proc. IEEE Int. Symp. EMC, 16-21, Aug. 2011. Google Scholar

22. Han, K. J., M. Swaminathan, and T. Bandyopadhyay, "Electromagnetic modeling of Through-Silicon Via (TSV) interconnections using cylindrical modal basis functions," IEEE Trans. Adv. Packag., Vol. 33, No. 4, 804-817, 2010.
doi:10.1109/TADVP.2010.2050769 Google Scholar

23. Ramo, S., J.Whinnery, and T. Duzer, Fields and Waves in Communication Electronics, 3rd Ed., Wiley, 1994.

24. Ndip, I., K. Zoschke, K. Lobbicke, M. J. Wolf, S. Guttowski, H. Reichl, K.-D. Lang, and H. Henke, "Analytical, numerical-, and measurement-based methods for extracting the electrical parameters of Through Silicon Vias (TSVs)," IEEE Trans. Compon. Packag. Manuf. Technol., Vol. 4, No. 3, 504-515, Mar. 2014.
doi:10.1109/TCPMT.2013.2279688 Google Scholar

25. Tsang, L., H. Braunisch, R. Ding, and X. Gu, "Random rough surface effects on wave propagation in interconnects," IEEE Trans. Adv. Packag., Vol. 33, No. 4, 839-856, Nov. 2010.
doi:10.1109/TADVP.2010.2089789 Google Scholar

26. http://www.ansys.com/Products/Simulation+Technology/Electronics/Signal+Integrity/ANSYS+HFSS.

27. Katti, G., M. Stucchi, K. de Meyer, and W. Dehaene, "Electrical modeling and characterization of through-silicon-via for three dimensional ICs," IEEE Trans. Electron Devices, Vol. 57, No. 1, 256-262, Jan. 2010.
doi:10.1109/TED.2009.2034508 Google Scholar

28. Sze, S. M., Physics of Semiconductor Devices, Wiley, 1981.

29. Wang, G., R. W. Dutton, and C. S. Rafferty, "Device level simulation of wave propagation along metal-insulator-semiconductor interconnects," IEEE Trans. Microwave Theory and Tech., Vol. 50, No. 4, 1127-1136, Apr. 2002.
doi:10.1109/22.993416 Google Scholar

30. Bandyopadhyay, T., K. J. Han, D. Chung, R. Chatterjee, M. Swaminathan, and R. Tummala, "Rigorous electrical modeling of Through Silicon Vias (TSVs) with MOS capacitance effects," IEEE Trans. CPMT, Vol. 1, No. 6, 893-903, Jun. 2011. Google Scholar

31. Katti, G., M. Stucchi, J. V. Olmen, K. de Meyer, and W. Dehaene, "Through-Silicon-Via capacitance reduction technique to benefit 3-D IN performance," IEEE Electron Dev. Lett., Vol. 31, No. 6, 549-551, Jun. 2001.
doi:10.1109/LED.2010.2046712 Google Scholar

32. He, X., W. Wang, and Q. Cao, "Crosstalk modeling and analysis of Through-Silicon-Via connection in 3D integration," PIERS Proceedings, 857-861, Taipei, Mar. 25-28, 2013. Google Scholar

Dr. Md Amimul Ehsan

Dr. Zhen Zhou

Dr. Yang Yi