volume | PIER Journals

Abstract

This study offers a reduced device count (RDC) asymmetrical cross-connected seventeen-level T-type (CT-type) inverter. The proposed approach contains eight power switches, four self-voltage balancing capacitors and two direct current (DC) sources. The recommended architecture reduces the necessity to generate negative half-cycle for an H-bridge, hence minimizing the voltage stress across the switches. The capacitor and DC sources are cascaded with the switches to produce desired number of levels. Because of its substantial autonomy and high voltage balancing capability, this design is particularly beneficial to the integration of renewable energy sources into the grid. Pulse width modulation based on the level-shifted approach provides gate driver signals for the inverter circuit. A comparative analysis is undertaken to validate the efficacy of the suggested topology, which is differentiated from previously published topologies based on the number of DC sources, capacitor count, switches, drivers, and total standing voltage. Finally, the viability of the proposed topology is investigated by the simulated results and is further verified by a laboratory prototype. The total harmonic distortion (THD) of the voltage and current is obtained as 7.2% and 1.3% respectively.

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Mr. Vinay Pathak

Dr. Kishor Thakre

Dr. Prateek Nigam