volume | PIER Journals

2009-08-20

The Optimal Number and Location of Grounded Vias to Reduce Crosstalk

Wen-Tzeng Huang,

Prof. Wen-Tzeng Huang

Computer and Information Engineering

Minghsin University of Science and Technology

Taiwan, ROC

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Chi-Hao Lu,

Dr. Chi-Hao Lu

National Taipei University of Technology

Taiwan

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Ding-Bing Lin

Prof. Ding-Bing Lin

Department of Electronic and Computer Engineering

National Taiwan University of Science and Technology

Taiwan

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Progress In Electromagnetics Research, Vol. 95, 241-266, 2009

doi:10.2528/PIER09071709

Abstract

Modern electronic products are increasingly based on high-speed, high-density circuitry operating at lower voltages. With such designs, the signal integrity (SI) in a poor printed circuit board layout is affected by noise and may become unstable. Crosstalk is a major source of noise that interferes with SI. Generally, crosstalk can be reduced by adding a guard trace between the victim and aggressor areas of the circuit. In addition, grounded vias can be added to the guard trace to help reduce crosstalk. Since a large number of grounded vias degrade the SI and reduce the flexibility of the circuit routing, we propose a method to calculate the optimal distance between grounded vias in the guard trace and determine the smallest number of vias required to achieve optimal performance in reducing crosstalk. We show by time-domain simulation that our method reduces the near-end crosstalk by 27.65% and the far-end crosstalk by more than 31.63% compared to the three-width rule. This is backed up by experimental results that show not only reductions of 34.49% and 37.55% for the near- and far-end crosstalk over time-domain, respectively, but also reductions of 2.1 dB and 3.3 dB for the near- and far-end crosstalk over the frequency-domain, respectively. Our results indicate that our method of optimal grounded vias has better performance than other methods.

Citation

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Wen-Tzeng Huang, Chi-Hao Lu, and Ding-Bing Lin, "The Optimal Number and Location of Grounded Vias to Reduce Crosstalk," Progress In Electromagnetics Research, Vol. 95, 241-266, 2009.
doi:10.2528/PIER09071709

References

1. Sharawi, M. S., "Practical issues in high speed PCB design," IEEE Potentials, Vol. 23, No. 2, 24-27, Apr./May 2004.
doi:10.1109/MP.2004.1289994

2. Montrose, M. I., EMC and the Printed Circuit Board: Design, Theory, and Layout Made Simple, IEEE Press, 1998.

4. Rossi, D., P. Angelini, C. Metra, G. Campardo, and G. Vanalli, "Risks for signal integrity in system in package and possible remedies," 13th IEEE European Test, 165-170, May 2008.

5. Novak, I., B. Eged, and L. Hatvani, "Measurement by vector-network analyzer and simulation of crosstalk reduction on printed board with additional center traces," IEEE Institute of Technology Conference, 269-274, Irvine, CA, 1993.

6. Novak, I., B. Eged, and L. Hatvani, "Measurement and simulation of crosstalk reduction by discrete discontinuities along coupled PCB traces," IEEE Transactions on Instrumentation and Measurement, Vol. 43, No. 2, 170-175, Apr. 1994.
doi:10.1109/19.293415

7. Ladd, D. N. and G. Costache, "SPICE simulation used to characterize the cross-talk reduction effect of additional tracks grounded with vias on printed circuit boards," IEEE Transaction on Circuits and Systems II, Vol. 39, 342-347, Jun. 1992.
doi:10.1109/82.145291

8. Cheng, Y. S., W. D. Guo, G. H. Shine, H. H. Cheng, C. C. Wang, and R. B. Wu, "Fewest vias design for microstrip guard trace by using overlying dielectric," IEEE Electrical Performance of Electronic Packaging, 321-324, Oct. 2008.

9. Suntives, A., A. Khajooeizadeh, and R. Abhari, "Using via fences for crosstalk reduction in PCB circuits," IEEE International Symposium on Electromagnetic Compatibility, Vol. 1, 34-37, Aug. 2006.

10. Lee, K., H. B. Lee, H. K. Jung, J. Y. Sim, and H. J. Park, "A serpentine guard trace to reduce the far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines," IEEE Transactions on Advanced Packaging, Vol. 31, No. 4, 809-817, Nov. 2008.

11. Hall, S. H., G. W. Hall, and J. A. McCall, High-speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, John-Wiley & Sons, 2000.

12. Young, B., "Digital Signal Integrity: Modeling and Simulations with Interconnects and Packages," Prentice-Hall, 2001.

13. Muthana, P. and H. Kroger, "Behavior of short pulses on tightly coupled microstrip lines and reduction of crosstalk by using overlying dielectric," IEEE Transactions on Advanced Packaging, Vol. 30, No. 3, 511-520, Aug. 2007.
doi:10.1109/TADVP.2007.898507

14. Cheng, D. K., Field and Wave Electromagnetics, 2 Ed., Addison-Wesley, 1989.

15. Sobol, H., "Applications of integrated circuit technology to microwave frequencies," Proceedings of the IEEE, 1200-1211, Aug. 1971.
doi:10.1109/PROC.1971.8365

16. "Advance Allegro PCB SI Techniques V15.2," Cadence, 2005.

17. Mbairi, F. D., W. P. Siebert, and H. Hesselbom, "On the problem of using guard traces for high frequency differential lines crosstalk reduction," IEEE Transactions on Components and Packaging Technologies, Vol. 30, No. 1, 67-74, Mar. 2007.
doi:10.1109/TCAPT.2007.892072