Deep Insight into
Channel Engineering of Sub-3 nm
-Node P-Type Nanosheet Transistors with a Quantum Transport Model
Based on a self-consistent Schrodinger-Poisson solver and top-of-the-barrier model, a quantum transport simulator of p-type gate-all-around nanosheet FET is developed. The effects of material (Si/Ge), stress, crystallographic orientation, and cross-sectional size are deeply explored by numerical simulations for the device performance at the sub-3 nm technology node. A strain-dependent 6-band k.p Hamiltonian is incorporated into the model for a more accurate calculation of E-k dispersion in the strain-perturbed valence band structure, where the curvature, energy shift, and splitting of subbands are investigated in detail for hole transport properties. Further, the effect of channel engineering is comprehensively analyzed, by evaluating density-of-states effective mass, average injection velocity, mobility, current density distributions, and the current-voltage characteristics. An effective performance improvement from 2GPa compressive stress is obtained in /(001) and /(001) channels, with a 7% enhancement of ON-current in Ge nanosheet FETs. While a wider channel cross-section improves the drive current by increasing the effective channel width, a smaller cross-sectional width yields an average increase up to 29% in the ON-state injection velocity due to stronger quantum confinement.