volume | PIER Journals

Abstract

Due to high-density routing under the CPU and DIMM areas, the original design of even and odd mode characteristic impedances changes. The occurrence of multi-drop problem between the CPU and memory chip causes over- and under-driven that reduce the eye opening. Furthermore, the different phase velocities of even- and odd-modes cause timing jitter at the receiver end. This paper proposes two steps to solve the complex issue of signal integrity for the multi-module memory bus. First, particle swarm optimization (PSO) is used to tune the characteristic impedance of the transmission line and on-die termination (ODT) values to improve transmission line impedance changes to obtain maximum power delivery. The fitness function of the algorithm is defined by selecting the minimum reflection coefficient at the driver side and maximum the transmission coefficient at the receiver side to reduce the over- and under-driven Second, the timing jitter can be reduced by placing a capacitor to compensate for the velocity difference caused by different propagation modes. Finally, signal integrity enhancements for the DDR3 are verified by measuring S parameters in the frequency domain and postprocessed eye diagrams in the time domain.

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Prof. Ding-Bing Lin

Dr. Feng-Nan Wu

Dr. Wen Sheng Liu

Mr. Chen Kuang Wang

Dr. Hsin-Yun Shih