volume | PIER Journals

Abstract

Due to high-density routing under the CPU and DIMM areas, the original design of even and odd mode characteristic impedances changes. The occurrence of multi-drop problem between the CPU and memory chip causes over- and under-driven that reduce the eye opening. Furthermore, the different phase velocities of even- and odd-modes cause timing jitter at the receiver end. This paper proposes two steps to solve the complex issue of signal integrity for the multi-module memory bus. First, particle swarm optimization (PSO) is used to tune the characteristic impedance of the transmission line and on-die termination (ODT) values to improve transmission line impedance changes to obtain maximum power delivery. The fitness function of the algorithm is defined by selecting the minimum reflection coefficient at the driver side and maximum the transmission coefficient at the receiver side to reduce the over- and under-driven Second, the timing jitter can be reduced by placing a capacitor to compensate for the velocity difference caused by different propagation modes. Finally, signal integrity enhancements for the DDR3 are verified by measuring S parameters in the frequency domain and postprocessed eye diagrams in the time domain.

1. Granberg, T., Handbook of Digital Techniques for High-Speed Design, Prentic Hall, 2004.

2. Rainal, A. J。, "Performance limits of electrical interconnections to a high-speed chip ," IEEE Trans. on Components, Packaging, and Manufacturing Technology, Vol. 11, 260-266, Sep. 1998.

3. Huang, W.-T., C.-H. Lu, and D.-B. Lin, "Design of suppressing crosstalk by vias of serpentine guard trace," PIERS Online, Vol. 6, No. 4, 360-364, 2010.

4. Huang, W.-T., C.-H. Lu, and D.-B. Lin, "The optimal number and location of ground vias to reduce crosstalk," Progress In Electromagnetics Research, Vol. 95, 241-266, 209.

5. Chen, H. and Y. X. Zhang, "A synthetic design of eliminating crosstalk within MTLS," Progress In Electromagnetics Research, Vol. 76, 211-221, 2007.

6. Sharma, R., T. Chakravarty, and A. B. Bhattacharyya, "Reduction of signal overshoots in highspeed interconnects using adjacent ground tracks," Journal of Electromagnetic Waves and Applications, Vol. 24, No. 7, 941-950, 2010.

7. Johnson, H. and M. Graham, High-Speed Signal Propagation, 616-634, Prentice-Hall, 2003.

8. Johnson, H. and M. Graham, "High-Speed Digital Design," Prentice-Hall, 1993, 223-248.

9. Chih-Hsien, L. and J. Shyh-Jye, "4/2 PAM pre-emphasis transmitter with combined driver and mux," Proc. Int. Conf. on Antennas and Propagation, Vol. 1, 334-337, Edinburgh, Apr. 1997.

10. Kim, J., E. Song, J. Kim, J. Kim, M. Sung, J. Kim, and B. So, "Design and analysis of improved multi-module memory bus using Wilkinson power divider," Proc. IEEE International Symposium on Electromagnetic Compatibility, 642-645, Portland, Aug. 2006.

11. Koizumi, N., I. Yoshihara, K. Yamamori, and M. Yasunaga, "Variable length segmental-transmission-line and its parameter optimization based on GA," Proc. IEEE Congress on Evolutionary Computation, 1576-1582, Sep. 2005.

12. Koizumi, N., I. Yoshihara, K. Yamamori, and M. Yasunaga, "Enhancement of the variable-length-transmission-line design method for multi-point optimization," Proc. IEEE Congress on Evolutionary Computation, 142-148, Vancouver, Jul. 2006.

13. Lee, J., S. Han, S. Y. Kim, J. Kang, K. Park, and J. Kih, "Crosstalk cancellation of DDR3 memory channel for over 1600 Mbps data rate," 20th International Zurich Symposium on Proc., 337-340, Zurich, Jan. 2009.

14. Lee, K., H. K. Jung, J. Y. Sim, and H. J. Park, "Reduction of transient far-end crosstalk voltage and jitter in DIMM connectors for DRAM interface," IEEE Microwave and Wireless Components Letters, Vol. 19, No. 1, 15-17, Jan. 2009.

15. Lee, K., H. B. Lee, H. K. Jung, J. Y. Sim, and H. J. Park, "A serpentine guard trace to reduce the far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines," IEEE Transactions on Advanced Packaging, Vol. 31, No. 4, 809-817, Nov. 2008.

16. Lee, K., H. K. Jung, H. J. Chi, H. J. Kwon, J. Y. Sim, and H. J. Park, "Serpentine microstrip lines with zero far-end crosstalk for parallel high-speed DRAM interfaces," IEEE Transactions on Advanced Packaging, Vol. 33, No. 2, 552-558, May 2010.

17. Eberhart, R. C. and Y. Shi, "Comparison between genetic algorithms and particle swarm optimization," Proc. 7th Annual Conference on Evolutionary Programming, 611-616, San Diego, May 1998.

18. Eberhart, R. C. and J. Kennedy, "A new optimizer using particle swarm theory," Proc. 6th International Symposium, Micro Machine and Human Science, 39-43, Oct. 1995.

19. Shi, Y. and R. C. Eberhart, "A modified particle swarm optimizer," Proc. IEEE International Conference on Evolutionary Computation, 69-73, Anchorage, May 1998.

20. JEDEC, , DDR3 SDRAM SPECIFICATION.

21. Birchak, J. R. and H. K. Haill, "Coupling coefficients for signal lines separated by ground lines on Pc boards," Proc. 1989 International Test Conference, 190-198, Washington, Aug. 1989.

22. Eudes, T., B. Ravelo, and A. Louis, "Transient response characterization of the high-speed interconnection RLCG-model for the signal integrity analysis," Progress In Electromagnetics Research, Vol. 112, 183-197, 2011.

Prof. Ding-Bing Lin

Dr. Feng-Nan Wu

Dr. Wen Sheng Liu

Mr. Chen Kuang Wang

Dr. Hsin-Yun Shih