1. Sathanur, A. V., V. Jandhyala, and H. Braunisch, "A hierarchical simulation flow for return-loss optimization of microprocessor package vertical interconnects," IEEE Trans. Advanced Packaging, Vol. 33, No. 4, 1021-1033, 2010.
doi:10.1109/TADVP.2010.2049490 Google Scholar
2. Wu, B., B. Brown, and E. Warner, "High density interconnect board design for wafer level packaging," IET Electronics Letters, Vol. 47, No. 20, 1137-1138, 2011.
doi:10.1049/el.2011.1422 Google Scholar
3. Li, Y. and V. Jandhyala, "Multiparameter sensitivity analysis of multiple coupled vias in board and package structures for early design and optimization," IEEE Trans. Advanced Packaging, Vol. 33, No. 4, 1003-1011, 2010.
doi:10.1109/TADVP.2010.2047723 Google Scholar
4. Holden, H., "Microvias effect on high-frequency signal integrity," Circuit World, Vol. 28, No. 3, 10-21, 2002.
doi:10.1108/03056120310418439 Google Scholar
5. Lee, Y. C., "CPW-to-stripline vertical via transitions for 60 GHz LTCC sop applications," Progress In Electromagnetics Research Letters, Vol. 2, 37-44, 2008.
doi:10.2528/PIERL07122805 Google Scholar
6. Wu, B. and L. Tsang, "Modeling multiple vias with arbitrary shape of antipads and pads in high speed interconnect circuits," IEEE Microwave and Wireless Comp. Lett., Vol. 19, No. 1, 12-14, 2009.
doi:10.1109/LMWC.2009.2034034 Google Scholar
7. Wu, B. and L. Tsang, "Signal integrity analysis of package and printed circuit board with multiple vias in substrate of layered dielectrics," IEEE Trans. Advanced Packaging, Vol. 33, No. 2, 510-516, 2010.
doi:10.1109/TADVP.2009.2026482 Google Scholar
8. Wu, B. and L. Tsang, "Full-wave modeling of multiple vias using differential signaling and shared antipad in multilayered high speed vertical interconnects," Progress In Electromagnetics Research, Vol. 97, 129-139, 2009.
doi:10.2528/PIER09091707 Google Scholar
9. Oo, Z. Z., E.-X. Liu, X. C. Wei, Y. Zhang, and E.-P. Li, "Cascaded microwave network approach for power and signal integrity analysis of multilayer electronic packages," IEEE Trans. Components, Packaging and Manufacturing Technology, Vol. 1, No. 9, 1428-1437, 2011.
doi:10.1109/TCPMT.2011.2143712 Google Scholar
10. Wu, B., X. Gu, L. Tsang, and M. B. Ritter, "Electromagnetic modeling of massively coupled through silicon vias for 3-D interconnects," Microw. Opt. Technol. Lett., Vol. 53, No. 6, 1204-1206, 2011.
doi:10.1002/mop.26021 Google Scholar
11. Ye, C. and B. Wu, Micro-via structure design for high performance integrated circuits, U.S. Patent 7649265, Jan. 19, 2010.
12. Huang, C. C., R. Kunze, and B.-T. Lee, Inductor, U.S. Patent 7474539B2, Jan. 6, 2009.
13. Chandrasekhar, A., S. Venkataraman, P. R. Patel, S. Chickamenahalli, R. J. Fite, and C. Gurumurthy, Forming a helical inductor, U.S. Patent 7474539B2, Jan. 6, 2009.